config_msl.h 2.2 KB

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  1. /*Configurate for headfile,Auto-Created */
  2. #define CONFIG_COMPONENTS
  3. #define CONFIG_TA_AGENT_ENABLE
  4. #define CONFIG_TA_CHANNEL_UDP {("10.5.226.213"),(1118),("02-21-16-31-20-81")}
  5. #define CONFIG_TA_CHANNEL_UDP_RESEND_COUNT (10)
  6. #define CONFIG_TA_CHANNEL_UDP_SEND_POLLING_COUNT (12000)
  7. #define CONFIG_TA_DEBUG_CONFIG
  8. #define CONFIG_TA_BP_NUM (64)
  9. #define CONFIG_CORE_CFG
  10. #define CONFIG_SMT_ENABLE
  11. #define CONFIG_SMT_IS_ENABLED (false)
  12. #define CONFIG_COMPONENTS_MODE
  13. #define CONFIG_MODE_MOS_MODE
  14. #define CONFIG_LOAD_MODE
  15. #define CONFIG_COMPONENTS_TARGET_SHELL
  16. #define CONFIG_CMD_PARAM_ADDR (0x3800000)
  17. #define CONFIG_COMPONENTS_ERROR_HANDLE
  18. #define CONFIG_LOG_EVENT_NUM (64)
  19. #define CONFIG_DEV_PRINK_ENABLE
  20. #define CONFIG_DRIVERS_PRINTK ("COM1")
  21. #define CONFIG_DRIVERS
  22. #define CONFIG_BASE_DEVICE
  23. #define CONFIG_DRIVERS_TIMER
  24. #define CONFIG_DRIVERS_TIMER_MSPERTICKS (1000)
  25. #define CONFIG_DRIVERS_SERIAL
  26. #define CONFIG_DRIVERS_SERIAL_UART {\
  27. {("COM1"),(DR_UART_NO_PARITY),(8),(115200),(1),(DR_UART_POLLING)},\
  28. {("COM2"),(DR_UART_NO_PARITY),(8),(115200),(1),(DR_UART_POLLING)},\
  29. }
  30. #define CONFIG_DRIVERS_SERIAL_UART_L1_COM1
  31. #define CONFIG_DRIVERS_SERIAL_UART_L1_COM2
  32. #define CONFIG_MM_TABLE {\
  33. {("SPIFLASH"),(0x0),(0x0),(0x20000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  34. {("IO2"),(0x20000000),(0x20000000),(0x10000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  35. {("IO3"),(0x30000000),(0x30000000),(0x10000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  36. {("PCI"),(0x40000000),(0x40000000),(0x40000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  37. {("MEM"),(0x80000000),(0x80000000),(0x8000000),(MM_DEFAULT_SYSTEM_ATTR),(0x1000)},\
  38. {("NET_BUFF"),(0x88000000),(0x88000000),(0x1000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  39. {("TFTP_BUFF"),(0x89000000),(0x89000000),(0x2000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  40. {("ETHER"),(0x8B000000),(0x8B000000),(0x1000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  41. {("TEMP"),(0x8E000000),(0x8E000000),(0x1000000),(MM_DEFAULT_SYSTEM_IOADDR_ATTR),(0x1000)},\
  42. {("MEM1"),(0x90000000),(0x90000000),(0x70000000),(MM_DEFAULT_SYSTEM_ATTR),(0x1000)},\
  43. {("NULL"),(0x0),(0x0),(0x0),(0),(0x0)} }